1. Field of the Invention
The present invention relates to high speed serial communications data transfers between integrated circuits or systems and more particularly to an improved serializer/deserializer circuit having built-in self-test capabilities that is configured for jitter sensitivity characterization of the clock and data recovery circuit. A method for characterizing jitter sensitivity is also disclosed.
2. Background of the Invention
In the field of serial communications data transfers between integrated circuits or systems, it is common practice to exchange data between two telecommunications systems, one being referred to as the local SERDES circuit and the other as the distant SERDES circuit, each incorporating a serializer/deserializer (SERDES) function. In each SERDES circuit, the receiving part is usually provided with a clock and data recovery (CDR) circuit connected in series with the deserializer circuit that is in charge of extracting a clock signal, referred to as the recovered clock herein-below, from the incoming serial data stream. On the other hand, the emitting part is organized around the serializer circuit. In the case of high speed serial data communications, the performance of the CDR circuit is intimately tied to its capacity to correctly recover the transmitted data when the data period varies with time (jitter). Therefore, the characterization of the sensitivity of the CDR circuit placed in the deserializer part of the SERDES circuit to the jitter is of prime importance for the user to assess the quality of the data transfer.
The jitter tolerance of the CDR circuit is usually not characterized in-situ as it requires a jittered data generator, a specialized and expensive piece of characterization equipment. In addition, when such characterization is performed before delivery to the customer, it usually involves a few samples of the total order because of the time required to complete it.
Moreover, the jittered data generator must produce a realistic data stream, i.e. a set of frames formatted according to the transmission protocol under consideration, e.g. SONET/SDH protocol, if the deserializer under test is not itself configured to characterize its performance.
Lastly, without a jittered data generator, it is generally impractical to evaluate in-situ the quality of a particular physical link between the local and distant serializer/deserializer circuits or to determine if the CDR circuit is still working as specified.
The capabilities of standard characterization test equipment to generate high frequency jittered data is typically limited to a small percentage of the data transmission rate. For instance, in the case of SONET/SDH test equipment, if the jitter rate is equal to 1% of the transmission rate, it represents a 6 MHz jitter for a data transmission rate of 622 Mbps. This situation is exacerbated for the test equipment used in the manufacturing lines, because they are usually not able to run at full speed. Conesequently, the CDR jitter tolerance is seldom verified at the manufacturing level.In summary, in the case of repeated losses of data or data corruption between distant serializer/deserializer circuits, an in-situ characterization of the CDR circuit jitter sensitivity is helpful in characterizing overall integrity of the communications network under consideration.
Published United States Patent Application No. 2001/0016929 A1 describes a built-in self-test (BIST) functional block that uses the serial loop back to test the CDR circuit operation in-situ. However the system and method described therein are limited to the functional test and cannot be used to assess and characterize the jitter immunity of the CDR circuit.
Commonly assigned U.S. Pat. No. 5,828,255 describes a method and circuit to reduce the jitter generated by a phase-locked loop (PLL) oscillator locked on a reference frequency by means of optimizing its operating range. However, this reference does not address the sensitivity of a CDR circuit to jittered data.
Finally, U.S. Pat. No. 5,563,921 proposes a method and circuits to detect and measure the jitter, but at the cost of requiring an additional PLL devoted to jitter detection. Moreover, there is no teaching as to a method of predicting whether data will be lost through the CDR circuit or whether the latter can recover the data with a sufficient margin.